By Frank Ghenassia
Currently hired at STMicroelectronics, Transactional-Level Modeling (TLM) places ahead a unique SoC layout technique past RTL with measured advancements of productiveness and primary time silicon luck.
The SystemC consortium has released the reputable TLM improvement package in may perhaps 2005 to standardize this modeling process. The library is versatile sufficient to version parts and structures at many alternative degrees of abstractions: from cycle-accurate to untimed versions, and from bit-true habit to floating-point algorithms. besides the fact that, cautious collection of the abstraction point and linked method is essential to make sure useful profits for layout teams.
Transaction-Level Modeling with SystemC provides the formalized abstraction and similar method outlined at STMicroelectronics, and covers all significant issues concerning the digital System-Level (ESL) industry:
- TLM modeling suggestions
- Early embedded software program improvement according to SoC digital prototypes
- useful verification utilizing reference versions
- structure research with combined TLM and cycle exact systems
- Unifying TLM and RTL with platform automation instruments
Complementary to the e-book, open resource code to place this strategy into perform is offered on a number of websites as indicated within the first chapter.
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Extra info for Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems
E. Instruction Set Simulator (ISS). This is an instruction-accurate model developed in C language at a higher level of abstraction. The co-existence of hardware and software during the SoC verification process is the essence of co-verification. While the hardware platform is connected to a logic simulator, a symbolic debugger links the associated software program to the ISS for its execution on the platform. Such cooperation offers a simultaneous controllability and visibility over both hardware and software to analyze the system behavior or performance.
It must leave users enough room to switch back to a purely untimed model for validation purposes. Furthermore, this intermediate model should never cover any functional information related to the microarchitecture such as FIFO, Finite State Machine (FSM) related to cycleaccurate behavior, or any other implementation-dependent features. Figure 2-5 illustrates the typical timelines of a process execution occurring in the untimed TLM. Two cases are demonstrated: a) Simulation without functional delays based on a functional specification that only defines sequences of actions.
Pulling all these factors together, raising the level of abstraction above RTL in the overall SoC design and verification flow has appeared to be a promising solution for the SoC industry. 2 Attempts at Raising Abstraction Level Bear in mind that any attempt made to raise the abstraction level is always a game of balancing the trade-off between the speed and accuracy of a potential simulation model. Our development effort has of course witnessed this game from tip to toe. Before tackling the subject of abstraction level, it is worth considering what the two extreme ends of the SoC design flow could offer.
Transaction Level Modeling with SystemC: TLM Concepts and Applications for Embedded Systems by Frank Ghenassia