By Andrea Cuomo (auth.), Jorge Juan Chico, Enrico Macii (eds.)
Welcome to the court cases of PATMOS 2003. This used to be the thirteenth in a sequence of foreign workshops held in numerous destinations in Europe. through the years, PATMOS has received acceptance as one of many significant ecu occasions dedicated to energy and timing features of built-in circuit and procedure layout. regardless of its signi?cant development and improvement, PATMOS can nonetheless be regarded as a truly casual discussion board, that includes high-level scienti?c shows including open discussions and panel periods in a unfastened and secure setting. This 12 months, PATMOS came about in Turin, Italy, geared up via the Politecnico di Torino, with technical co-sponsorship from the IEEE Circuits and structures Society and the beneficiant help of the ecu fee, in addition to that of numerous business sponsors, together with BullDAST, Cadence, Mentor photos, STMicroelectronics, and Synopsys. the target of the PATMOS workshop is to supply a discussion board to debate and examine the rising difficulties in methodologies and instruments for the layout of recent generations of built-in circuits and platforms. an important emphasis of the technical software is on velocity and low-power facets, with specific regard to modeling, characterization, layout, and architectures.
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Extra resources for Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003. Proceedings
Despain. Saving power in the control path of embedded processors. IEEE Design and Test of computers, 11(4):24–30, 1994. 9. Neil H. West and Kamran Eshraghian. Principles of CMOS VLSI Design. Addison Wesley, 1998. State Encoding for Low-Power FSMs in FPGA Luis Mengibar, Luis Entrena, Michael G. Lorenz, and Raúl Sánchez-Reillo Electronic Technology Department Universidad Carlos III de Madrid. Spain. es Abstract. In this paper, we address the problem of state encoding of FPGAbased Finite State Machines (FSMs) for low power dissipation.
The strategy, called Genetic Encoder Generator (GEG) has been compared with the most eﬀective techniques proposed in the literature. The results obtained on a set of speciﬁc applications for embedded systems have demonstrated the superiority of our approach, with savings of around 50% on multiplexed address buses (instructions/data) and close to 45% on instruction address buses. In the latter case the T0 scheme  performs better than the approach proposed here, with average savings of 70%. A mixed technique GEG+T0 (in which a GEG and T0 works concurrently) further enhances the eﬃciency of T0, achieving average savings of 80%.
143, No. it Abstract. In this paper we present a genetic approach for the eﬃcient generation of an encoder to minimize switching activity on the highcapacity lines of a communication bus. The approach is a static one in the sense that the encoder is realized ad hoc according to the traﬃc on the bus. The approach refers to embedded systems in which it is possible to have detailed knowledge of the trace of the patterns transmitted on a bus following execution of a speciﬁc application. The approach is compared with the most eﬃcient encoding schemes proposed in the literature on both multiplexed and separate buses.
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 13th International Workshop, PATMOS 2003, Turin, Italy, September 10-12, 2003. Proceedings by Andrea Cuomo (auth.), Jorge Juan Chico, Enrico Macii (eds.)