By Kerry Bernstein, K.M. Carrig, Christopher M. Durham, Patrick R. Hansen, David Hogenmiller, Edward J. Nowak, Norman J. Rohrer
High velocity CMOS layout Styles is written for the graduate-level scholar or working towards engineer who's essentially drawn to circuit layout. it truly is meant to supply sensible reference, or `horse-sense', to mechanisms generally defined with a extra educational slant. This booklet is geared up in order that it may be used as a textbook or as a reference booklet.
High velocity CMOS layout Styles offers a survey of layout kinds in use in undefined, particularly within the excessive velocity microprocessor layout neighborhood. good judgment circuit buildings, I/O and interface, clocking, and timing schemes are reviewed and defined. features, sensitivities and idiosyncrasies of every are highlighted. High SpeedCMOS layout Styles additionally pulls jointly and explains members to functionality variability which are linked to approach, purposes stipulations and layout. ideas of thumb and useful references are provided. all of the normal circuit households is then analyzed for its sensitivity and reaction to this variability.
High velocity CMOS layout Styles is a superb resource of rules and a compilation of observations that spotlight how various techniques alternate off severe parameters in layout and approach space.
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Extra resources for High Speed CMOS Design Styles
Rule of thumb: For process technologies designed near the scaling limit for their power supply, when VDD is increased (to achieve higher performance) by more than about 20% above the nominal operating voltage for the technology, the end-of-life performance can actually decrease rather than increase, as the performance improvement from higher supply voltage is exceeded by the wearout caused by that voltage. Hot carrier degradation is a reliability consideration. Because of the complexity required to determine how much each circuit will slow down, it is not practical to retime a design with each circuit's specific degraded performance.
Standby current, or Ioo(quiescent), is the DC power consumption of the chip when the clocks are not running, and the part is stopped at a particular machine state. 1 Subthreshold Leakage Currents "A nanoAmp here, a nanoAmp there, pretty soon that's a lot of Cllrrent " Simple device models depicting the MOSFET in its linear region suggest los goes to zero for gate biases under the threshold voltage. This is, in fact, not true in actual hardware. In the subthreshold region of device operation, the drain-to-source current has an exponential dependence on gate voltage.
26 shows a scanning-electron-microscope photograph of an electromigration casualty intentionally caused by microprocessor stress. 26 SEM photo of electromigration occurrence on conductor (from P. C. Li and T. K. 75, © IEEE 1996) Rule of thumb: Although severe EM can cause virtually complete opens on aluminum wires, assume lone interconnects may degrade in resistance by up to 10% by End-of-Life for in applications with high current densities. Because the voiding is driven by electron drift, conductors with AC current are believed to be at less risk for EM damage, but are still vulnerable to damage caused by local Joule heating.
High Speed CMOS Design Styles by Kerry Bernstein, K.M. Carrig, Christopher M. Durham, Patrick R. Hansen, David Hogenmiller, Edward J. Nowak, Norman J. Rohrer