By Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng
This booklet offers vast and entire assurance of the whole EDA circulate. EDA/VLSI practitioners and researchers wanting fluency in an "adjacent" box will locate this a useful connection with the elemental EDA strategies, rules, information constructions, algorithms, and architectures for the layout, verification, and try of VLSI circuits. somebody who must study the strategies, rules, facts buildings, algorithms, and architectures of the EDA movement will take advantage of this book.Covers whole spectrum of the EDA stream, from ESL layout modeling to logic/test synthesis, verification, actual layout, and attempt - is helping EDA novices to get "up-and-running" speedy comprises accomplished insurance of EDA options, rules, facts constructions, algorithms, and architectures - is helping all readers enhance their VLSI layout competence includes most up-to-date developments now not but on hand in different books, together with try compression, ESL layout modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - is helping readers to design/develop testable chips or items contains best-practices anywhere applicable in so much chapters - is helping readers stay away from expensive blunders
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Extra info for Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon)
Logic simulation is used throughout every stage of logic design automation, whereas circuit simulation is used after physical design. 2 Logic design automation event-driven simulation [Wang 2006]. The former is most effective for cyclebased two-valued simulation; the latter is capable of handling various gate and wire delay models. Although versatile and low in cost, logic simulation is too slow for complex SOC designs or hardware/software co-simulation applications. For more accurate timing information and dynamic behavior analysis, devicelevel circuit simulation is used.
8. Before technology mapping, however, a number of technologyindependent optimizations can be made to the gate-level implementation by basic logic restructuring with techniques such as the Quine-McCluskey method for two-level logic optimization [McCluskey 1986] or methods for multilevel logic optimization that may be more appropriate for standard cell–based designs [Brayton 1984; De Michele 1994; Devadas 1994]. Once technology mapping has been performed, additional optimizations are performed such as for timing and power.
Another is the design time to meet the market window and development cost goals. The potential risk to the project in obtaining a working, cost-effective product on schedule is an extremely important design issue that also hinges on reuse of resources (using the same core in different modes of operation, for example) and the target implementation media and its associated technology limits. Less frequently addressed, but equally important, design considerations include designer experience and EDA software availability and capabilities.
Electronic Design Automation: Synthesis, Verification, and Test (Systems on Silicon) by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng