Francis C. Wang's Digital Circuit Testing. A Guide to DFT and Other Techniques PDF

By Francis C. Wang

ISBN-10: 0127345809

ISBN-13: 9780127345802

Contemporary technological advances have created a trying out hindrance within the electronics industry--smaller, extra hugely built-in digital circuits and new packaging recommendations make it more and more tough to bodily entry try nodes. New checking out equipment are wanted for the subsequent iteration of digital apparatus and loads of emphasis is being put on the advance of those tools. the various thoughts now changing into renowned comprise layout for testability (DFT), integrated self-test (BIST), and automated try out vector new release (ATVG). This ebook will offer a pragmatic advent to those and different checking out suggestions. for every method brought, the writer presents real-world examples so the reader can in attaining a operating wisdom of ways to decide on and practice those more and more vital checking out equipment.

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Additional info for Digital Circuit Testing. A Guide to DFT and Other Techniques

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However, the resolutions of sensitivities are generally lost while test counts propagate through a fanout node due to the following reasons. 1. Self masking: The setting of sensitive value on a branch can be masked by the setting on the other branches. This can make the stem insensitive while the branches are sensitive. 9 Fanout and reconvergent node. 3 Sensitivity Analysis at a Fanout Node 47 2. Multiple-path sensitization: Some faults require propagation of fault effect along multiple paths for detection.

In this block, it is determined whether the driving lead is an input to an XOR gate, an input to another type of gate, or Chapter 2. 13 Flowchart for fanout handling: Redundancy detection. 14 Flowchart for fanout handling: Loop enumeration. 15 Flowchart for fanout handling: Sensitivity forward drive and reconvergent gate handling. 4 55 Local Enumeration Technique Θ oΘ £> Θ o Θ £> 1" Θ S^. 16 Forward sensitivity drive requirements for different gates. an inner fanout loop. In the third instance, if the driving lead is part of an outer reconvergent fanout loop encompassing an inner loop which has already been enumerated, then a suitable partial solution which is consistent with the present solution is taken.

The following equation expresses this constraint or relationship mathematically. 4 Test values for an AND gate. 42 Chapter 2. A Test Generation Method Using Testability Results On the other hand, whenever one input lead is required to be 1 + , the output and the other input leads must all be 1 + in order to satisfy the definition of sensitive value given earlier. Hence, Ct ^ Max(Ar,5i + ) (2) Equations (1) and (2) are the constraints for test count forward propagation through an AND gate. Backward propagation also affects test counts.

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Digital Circuit Testing. A Guide to DFT and Other Techniques by Francis C. Wang


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