By Jose M. de la Rosa, Rocio del Rio(auth.)
A entire evaluation of Sigma-Delta Analog-to-Digital Converters (ADCs) and a realistic consultant to their layout in nano-scale CMOS for optimum performance.
This e-book offers a scientific and finished compilation of sigma-delta converter working ideas, the hot advances in architectures and circuits, layout methodologies and functional concerns ? going from system-level necessities to silicon integration, packaging and meaurements, with emphasis on nanometer CMOS implementation. The publication emphasizes useful layout concerns – from high-level behavioural modelling in MATLAB/SIMULINK, to circuit-level implementation in Cadence layout FrameWork II. in addition to being a entire connection with the idea, the e-book is additionally exact in that it offers specific significance on functional matters, giving a close description of the several steps that represent the entire layout stream of sigma-delta ADCs.
The publication starts off with an introductory survey of sigma-delta modulators, their basics architectures and synthesis tools coated in bankruptcy 1. In bankruptcy 2, the impression of major circuit blunders mechanisms is analysed, supplying the mandatory realizing of the most sensible matters affecting the functionality of sigma-delta modulators. the data derived from the 1st chapters is gifted within the booklet as a vital a part of the systematic top-down/bottom-up synthesis method of sigma-delta modulators defined in bankruptcy three, the place a time-domain behavioural simulator named SIMSIDES is defined and utilized to the high-level layout and verification of sigma-delta ADCs. bankruptcy four strikes farther down from system-level to the circuit and actual point, offering a few layout strategies and sensible recipes to accomplish the layout stream of sigma-delta modulators. To finish the publication, bankruptcy five supplies an summary of the cutting-edge sigma-delta ADCs, that are exhaustively analysed for you to extract useful layout guidance and to spot the incoming traits, layout demanding situations in addition to functional ideas proposed by way of state-of-the-art designs.
• deals a whole survey of sigma-delta modulator architectures from basics to state-of-the paintings topologies, contemplating either switched-capacitor and continuous-time circuit implementations
• supplies a scientific research and functional layout consultant of sigma-delta modulators, from a top-down/bottom-up standpoint, together with mathematical versions and analytical methods, behavioural modeling in MATLAB/SIMULINK, macromodeling, and circuit-level implementation in Cadence layout FrameWork II, chip prototyping, and experimental characterization.
• Systematic compilation of state of the art sigma-delta modulators
• whole description of SIMSIDES, a time-domain behavioural simulator carried out in MATLAB/SIMULINK
• lots of examples, case reviews, and simulation try out benches, overlaying the several levels of the layout circulate of sigma-delta modulators
• a few digital assets, together with SIMSIDES, the statistical information utilized in the state of the art survey, in addition to many layout examples and try benches are hosted on a significant other website
Essential interpreting for Researchers and electronics engineering practitioners drawn to the layout of high-performance facts converters built-in in nanometer CMOS applied sciences mixed-signal designers.
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Additional resources for CMOS Sigma-Delta Converters: Practical Design Guide
N − 1) and BN = B. 50) N −1 (L−LN ) (1 − z ) EDAC (z), with L = Li i=1 if the error in the back-end multibit DAC EDAC (z) is taken into account in the linear analysis. Many cascade M integrated circuits using this dual-quantization scheme can be found in the literature [4, 10, 18]. Many cascade Ms employing multibit quantization in all stages have also been reported [51, 67]. Note that, under ideal conditions, the quantization errors of all but the last stage are canceled at the overall cascade output by the DCL.
8b. Errors related to the multibit conversion are added to the quantization error e that has been considered so far; namely, an error eADC associated to the A/D conversion and an error eDAC in the subsequent D/A conversion required to reconstruct the analog feedback signal. Note that eADC is injected in the same path as the quantization error e and, therefore, it is also attenuated within the signal band by noise shaping. However, DAC errors are injected in the feedback path and, therefore, they directly add to the M input signal and pass to the M output as part of the input signal itself.
The described concept of unity STF can be extended to a noise shaping of any order. The only requirement is to ideally make STF(z) = 1, without changing the modulator NTF. In recent years, it has been often applied in Ms for wideband and multimode applications [30–34]. 2 High-Order Ms The simplest way to extend a M to an arbitrary Lth-order shaping consists of including L integrators before the quantizer. 16. 18 High-order single-loop M with distributed feedback. 26 for the second-order M. 13, respectively.
CMOS Sigma-Delta Converters: Practical Design Guide by Jose M. de la Rosa, Rocio del Rio(auth.)