By Paul R. Gray
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Extra resources for Analysis and Design of Analog Integrated Circuits
The internal base node is labeled B' to distinguish it from the external base contact B. The capacitance C, contains the base-charging capacitance C. and the emitter-base depletion layer capacitance C j , . Note that the representation of parasitics in Fig. 20 is an approximation in that lumped elements have been used. In practice, as suggested by Fig. 19, C, is distributed across r b and C,, is distributed across r,. This lumped representation is adequate for most purposes but can introduce errors at very high frequencies.
One way to achieve these goals is to use a processing technology that provides both bipolar and MOS transistors, allowing great design flexibility. However, all-MOS processes are less expensive than combined bipolar and MOS processes. Therefore, economic considerations drive integrated-circuit manufacturers to use all-MOS processes in many practical cases. As a result, the study of the characteristics of MOS transistors that affect analog integrated-circuit design is important. 1 Transfer Characteristics of MOS Devices A cross section of a typical enhancement-mode n-channel MOS (NMOS) transistor is shown in Fig.
Region 111 is the high-current region, where PF decreases as Ic increases. The reasons for this behavior of PF with IC can be better appreciated by plotting base current IB and collector current Ic on a log scale as a function of V e E . This is shown in Fig. 16, and because of the log scale on the vertical axis, the value of In PF can be obtained directly as the distance between the two curves. At moderate current levels represented by region I1 in Figs. 48). 82), and the decrease in PF is due to an additional component in IB, which is mainly due to recombination of carriers in the base-emitter depletion region and is present at any current level.
Analysis and Design of Analog Integrated Circuits by Paul R. Gray